# Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems
> Samman F.A.

URL kanonis: https://discover.unhas.ac.id/publications/reconfigurable-streaming-processor-core-with-interconnected-floating-point-arith
Jurnal / Konferensi: 6th International Workshop on Reconfigurable Communication Centric Systems on Chip Recosoc 2011 Proceedings
Tahun terbit: 2011
DOI: https://doi.org/10.1109/ReCoSoC.2011.5981539
Citations: 2

## Authors
- Samman F.A.

## Abstract
A reconfigurable and programmable streaming processor core complemented with interconnected arithmetic units for the acceleration of floating-point operations is presented in this paper. The streaming processor can be easily reconfigured to perform a complex scientific algorithm or computations by changing the set of instructions in a central control unit. By using floating-point arithmetic unit with pipeline streaming data flow, floating-point operations can be performed in each cycle resulting in a high-performance scientific computations. The streaming processor is dedicated for a high-performance adaptive signal processing applications. For higher performance, reliability and fault-tolerance scientific computations, the streaming processor would be designed as a tile processor in a multicore streaming processor system.

## Keywords
- Computer science
- Multi-core processor
- Pipeline (software)
- Arithmetic logic unit
- Floating point
- Digital signal processor
- Parallel computing
- Floating-point unit
- Computation
- Stream processing
- Instruction set
- Computer hardware
- Embedded system
- Digital signal processing
- Operating system
- Algorithm

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Sumber: Discover Unhas — RIMS Universitas Hasanuddin.
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