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Enhancing Computational Efficiency: Transitioning from Serial to Parallel Programming for Low-to-High Resolution Video Reconstruction Using FSRCNN on AMP Architecture
Annisa
2025 IEEE International Conference on Artificial Intelligence and Mechatronics Systems Aims 2025
Abstract
Super Resolution (SR) video has become a major concern in the image processing community, as increasing video resolution from low to high still faces various challenges. This research aims to improve the performance of the FSRCNN program on asymmetric multicore processors by leveraging the advantages of the big.LITTLE architecture. By converting a serial program to parallel, processors can operate and access shared data simultaneously, thereby potentially increasing the computational speed that is often bottlenecked at certain stages in the program, which can also affect video pixel accuracy. The results showed that the parallel scenario using 4 big CPUs produced the best video quality with the fastest computation time compared to the other scenarios. In contrast, the worst scenario occurs when using 4 LITTLE CPUs, which results in the longest computation time and lower video quality with the appearance of more artifacts. Meanwhile, the hybrid scenario (big.LITTLE and LITTLE.big, 8 threads) offers a balance between performance and video quality, although it still cannot rival the results obtained with big CPUs. The main factors affecting the computation time in FSRCNN are the use of LITTLE CPUs as well as the processing bottleneck at layer 8 (deconvolution stage), which shows the least speedup in the parallel scenario.