Design and Validation of Asynchronous Inter FPGA Transceivers for Inter Processor Communication

Abstract

Design, implementation and testing of a high performance asynchronous inter processor communications in physical layers are presented in this paper. The performances of two asynchronous communication interface transceivers, namely a bit-level parallel handshaking interface (PHI) and a source synchronous interface (SSI) transceiver, are exposed. The both transceivers have been modeled in VHDL, implemented and tested on Cyclone III FPGA. They can be operated at 50 MHz frequency clock and there is no data loses during communications. The performance measurement results shows that the single-bit SSI transceiver can reach end-to-end baud rate of about 4 Mbps for 8-bit data burst. The proposed PHI transceiver meanwhile can reach end-to-end baud rate of about 229 Mbps for 32-bit data burst and 50 MHz clock frequency. However, for short streams of data with working frequency of 50 Mhz, both interfaces can reach higher link-to-link baud-rate.

Access to Document

Other files and links

• Link to publication in Scopus

Fingerprint